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2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 1 of 75 product description the kx022 is a tri - axis 2g, 4g or 8g silicon micromachined accelerometer with integrated 256 byte buffer, orientation, tap/double tap, and activity detecting algorithms. the sense element is fabricated using kionixs proprietary p lasma micromachining process technology. acceleration sensing is based on the principle of a differential capacitance arising from acceleration - induced motion of the sense element, which further utilizes common mode cancellation to decrease errors from pr ocess variation, temperature, and environmental stress. the sense element is hermetically sealed at the wafer level by bonding a second silicon lid wafer to the device using a glass frit. a separate asic device packaged with the sense element provides si gnal conditioning, and intelligent user - programmable application algorithms. the accelerometer is delivered in a 2 x 2 x 0.9 mm lga plastic package operating from a 1.8 C 3.6v dc supply. voltage regulators are used to maintain constant internal operating voltages over the range of input supply voltages. this results in stable operating characteristics over the range of input supply voltages and virtually undetectable ratiometric error. i 2 c or spi digital protocol is used to communicate with the chip to configure and check for updates to the orientation, directional tap tm detection and activity monitoring algorithms. features ? 2 x 2 x 0.9 mm lga ? user - selectable g range and output data rate ? user - selec table low power or high resolution mode ? digital high - pas s filter outputs ? embedded fifo/filo buffer ? low power consumption with fl exset? performance optimization ? internal voltage regulator ? enhanced integrated directional tap/double - tap tm , and device - orientation algorithms ? user - configurable wake - up function ? digita l i 2 c up to 3.4mhz ? digital spi up to 10mhz ? lead - free solderability ? excellent temperature performance ? high shock survivability ? factory programmed offset and sensitivity ? self - test function
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 2 of 75 table of contents product description ................................ ................................ ................................ ................................ ................................ .... 1 features ................................ ................................ ................................ ................................ ................................ ......................... 1 table of contents ................................ ................................ ................................ ................................ ................................ ......... 2 functional diagram ................................ ................................ ................................ ................................ ................................ .... 5 produ ct specifications ................................ ................................ ................................ ................................ ................................ 6 m echanical ................................ ................................ ................................ ................................ ................................ ............................ 6 e lectrical ................................ ................................ ................................ ................................ ................................ ............................... 7 start up time profile ................................ ................................ ................................ ................................ ................................ ........ 8 cur rent profile ................................ ................................ ................................ ................................ ................................ .................. 8 power - on procedure ................................ ................................ ................................ ................................ ................................ ......... 9 e nvironmental ................................ ................................ ................................ ................................ ................................ ..................... 10 t erminology ................................ ................................ ................................ ................................ ................................ ........................ 11 g ................................ ................................ ................................ ................................ ................................ ................................ ...... 11 sensitivity ................................ ................................ ................................ ................................ ................................ ........................ 11 zero - g offset ................................ ................................ ................................ ................................ ................................ ................... 11 self - test ................................ ................................ ................................ ................................ ................................ ........................... 11 f unctionality ................................ ................................ ................................ ................................ ................................ ....................... 12 sense element ................................ ................................ ................................ ................................ ................................ ................. 12 asic interface ................................ ................................ ................................ ................................ ................................ ................. 12 factory calibration ................................ ................................ ................................ ................................ ................................ .......... 12 a pplication s chematic ................................ ................................ ................................ ................................ ................................ .......... 13 p in d escriptions ................................ ................................ ................................ ................................ ................................ ................... 13 t est s pecifications ................................ ................................ ................................ ................................ ................................ ................ 14 p ackage d imensions and o rientatio n ................................ ................................ ................................ ................................ ................... 15 dimensions ................................ ................................ ................................ ................................ ................................ ..................... 15 orientation ................................ ................................ ................................ ................................ ................................ ..................... 16 digital interface ................................ ................................ ................................ ................................ ................................ ......... 18 i 2 c s erial i nterface ................................ ................................ ................................ ................................ ................................ ............... 18 i 2 c operation ................................ ................................ ................................ ................................ ................................ .................. 19 writing to 8 - bit register ................................ ................................ ................................ ................................ ................................ . 20 reading from 8 - bit register ................................ ................................ ................................ ................................ ............................ 20 data transfer sequences ................................ ................................ ................................ ................................ ................................ 21 hs - mode ................................ ................................ ................................ ................................ ................................ ......................... 22 i 2 c timing diagram ................................ ................................ ................................ ................................ ................................ ......... 23 spi c ommunications ................................ ................................ ................................ ................................ ................................ ............. 24 4 - wire spi interface ................................ ................................ ................................ ................................ ................................ ........ 24 4 - wire spi timing diagram ................................ ................................ ................................ ................................ ............................ 25 4 - wire read and write registers ................................ ................................ ................................ ................................ ................... 26 3 - wire spi interface ................................ ................................ ................................ ................................ ................................ ........ 27 3 - wire spi timing diagram ................................ ................................ ................................ ................................ ............................ 28
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 3 of 75 3 - wire read and write regis ters ................................ ................................ ................................ ................................ ................... 29 embedded registers ................................ ................................ ................................ ................................ ................................ .... 30 a ccelerometer o utputs ................................ ................................ ................................ ................................ ................................ ........ 31 xhp_l ................................ ................................ ................................ ................................ ................................ ................................ .. 32 xhp_h ................................ ................................ ................................ ................................ ................................ ................................ . 32 yhp_l ................................ ................................ ................................ ................................ ................................ ................................ .. 32 yhp_h ................................ ................................ ................................ ................................ ................................ ................................ . 32 zhp_l ................................ ................................ ................................ ................................ ................................ ................................ .. 33 zhp_h ................................ ................................ ................................ ................................ ................................ ................................ . 33 xout_l ................................ ................................ ................................ ................................ ................................ ............................... 33 xout_h ................................ ................................ ................................ ................................ ................................ ............................... 33 yout_l ................................ ................................ ................................ ................................ ................................ ............................... 34 yout_h ................................ ................................ ................................ ................................ ................................ ............................... 34 zout_l ................................ ................................ ................................ ................................ ................................ ................................ 34 zout_h ................................ ................................ ................................ ................................ ................................ ............................... 34 cotr ................................ ................................ ................................ ................................ ................................ ................................ ... 35 who_am_i ................................ ................................ ................................ ................................ ................................ ......................... 35 tscp ................................ ................................ ................................ ................................ ................................ ................................ .... 35 tspp ................................ ................................ ................................ ................................ ................................ ................................ .... 36 ins1 ................................ ................................ ................................ ................................ ................................ ................................ ..... 36 ins2 ................................ ................................ ................................ ................................ ................................ ................................ ..... 37 ins3 ................................ ................................ ................................ ................................ ................................ ................................ ..... 38 status_reg ................................ ................................ ................................ ................................ ................................ ....................... 38 int_rel ................................ ................................ ................................ ................................ ................................ ............................... 38 cntl1 ................................ ................................ ................................ ................................ ................................ ................................ .. 39 cntl2 ................................ ................................ ................................ ................................ ................................ ................................ .. 40 cntl3 ................................ ................................ ................................ ................................ ................................ ................................ .. 41 odcntl ................................ ................................ ................................ ................................ ................................ ............................... 43 inc1 ................................ ................................ ................................ ................................ ................................ ................................ .... 44 inc2 ................................ ................................ ................................ ................................ ................................ ................................ .... 44 inc3 ................................ ................................ ................................ ................................ ................................ ................................ .... 45 inc4 ................................ ................................ ................................ ................................ ................................ ................................ .... 45 inc5 ................................ ................................ ................................ ................................ ................................ ................................ .... 46 inc6 ................................ ................................ ................................ ................................ ................................ ................................ .... 46 tilt_timer ................................ ................................ ................................ ................................ ................................ ......................... 47 wufc ................................ ................................ ................................ ................................ ................................ ................................ .. 47 tdtrc ................................ ................................ ................................ ................................ ................................ ................................ .. 47 tdtc ................................ ................................ ................................ ................................ ................................ ................................ .... 48 tth ................................ ................................ ................................ ................................ ................................ ................................ ...... 48 ttl ................................ ................................ ................................ ................................ ................................ ................................ ....... 49 ftd ................................ ................................ ................................ ................................ ................................ ................................ ...... 49 std ................................ ................................ ................................ ................................ ................................ ................................ ...... 49 tlt ................................ ................................ ................................ ................................ ................................ ................................ ....... 50
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 4 of 75 tws ................................ ................................ ................................ ................................ ................................ ................................ ..... 50 ath ................................ ................................ ................................ ................................ ................................ ................................ ..... 51 tilt_angle_ll ................................ ................................ ................................ ................................ ................................ ................... 51 tilt_angle_hl ................................ ................................ ................................ ................................ ................................ ................... 51 hyst_set ................................ ................................ ................................ ................................ ................................ ............................ 52 lp_cntl ................................ ................................ ................................ ................................ ................................ .............................. 52 buf_cntl1 ................................ ................................ ................................ ................................ ................................ ......................... 53 buf_cntl2 ................................ ................................ ................................ ................................ ................................ ......................... 54 buf_status_1 ................................ ................................ ................................ ................................ ................................ ................... 55 buf_status_2 ................................ ................................ ................................ ................................ ................................ ................... 55 buf_clear ................................ ................................ ................................ ................................ ................................ ......................... 55 buf_read ................................ ................................ ................................ ................................ ................................ ........................... 55 self_test ................................ ................................ ................................ ................................ ................................ ........................... 56 embedded application s ................................ ................................ ................................ ................................ ............................. 57 o rientation d etection f eature ................................ ................................ ................................ ................................ ............................. 57 hysteresis ................................ ................................ ................................ ................................ ................................ ........................ 57 device orientation angle (aka tilt angle) ................................ ................................ ................................ ................................ ....... 58 tilt timer ................................ ................................ ................................ ................................ ................................ ......................... 59 m otion i nterrupt f eature d escription ................................ ................................ ................................ ................................ ................. 60 d irectional t ap d etection f eature d escription ................................ ................................ ................................ ................................ ..... 62 perform ance index ................................ ................................ ................................ ................................ ................................ .......... 62 single tap detection ................................ ................................ ................................ ................................ ................................ ....... 63 double tap detection ................................ ................................ ................................ ................................ ................................ ..... 64 s ample b uffer f eature d escription ................................ ................................ ................................ ................................ ....................... 65 fifo mode ................................ ................................ ................................ ................................ ................................ ...................... 65 stream mode ................................ ................................ ................................ ................................ ................................ .................. 65 trigger mode ................................ ................................ ................................ ................................ ................................ .................. 66 filo mode ................................ ................................ ................................ ................................ ................................ ...................... 66 buffer operation ................................ ................................ ................................ ................................ ................................ ............. 66 notice ................................ ................................ ................................ ................................ ................................ ............................ 72 p recaution on using kionix p roducts ................................ ................................ ................................ ................................ ................. 72 p recaution for m ounting / c ircuit board design ................................ ................................ ................................ ................................ .. 73 p recautions r egarding a pplication e xamples and e xternal c ircuits ................................ ................................ ................................ ..... 73 p recaution for e lectrostatic ................................ ................................ ................................ ................................ ............................... 73 p recaution for s torage / t ransportation ................................ ................................ ................................ ................................ ............ 73 p recaution for p roduct l abel ................................ ................................ ................................ ................................ .............................. 74 p recaution for d ispositio n ................................ ................................ ................................ ................................ ................................ ... 74 p recaution for f oreign e xchange and f oreign t rade act ................................ ................................ ................................ ...................... 74 p recaution r egarding i ntellectual p roperty r ights ................................ ................................ ................................ ............................. 74 o ther p recaution ................................ ................................ ................................ ................................ ................................ ................. 74 g eneral p recaution ................................ ................................ ................................ ................................ ................................ ............. 74 revision history ................................ ................................ ................................ ................................ ................................ .......... 75
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 5 of 75 functional diagram z accel y accel adc i 2 c/spi interface dsp power x accel fifo buffer amplifier vdd gnd io vdd sda scl addr int1 trig sdo ncs int2
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 6 of 75 product specifications mechanical ( specifications are for operation at vdd = 2.5 v and t = rt = 25 c unless stated otherwise) parameters units min typical max operating te mperature range c - 40 - 85 zero - g offset mg 25 90 zero - g offset variation from rt over temp. mg/ c 0.2 sensitivity 1 gsel1=0, gsel0=0 ( 2g) counts/g 15401 16384 17367 gsel1=0, gsel0=1 ( 4g) 7700 8192 8684 gsel1=1, gsel0=0 ( 8g) 3850 4096 4342 sensitivity ( buffer 8 - bit mode ) 1,2 gsel1=0, gsel0=0 ( 2g) counts/g 60 64 68 gsel1=0, gsel0=1 ( 4g) 30 32 34 gsel1=1, gsel0=0 ( 8g) 15 16 17 sensitivity variation from rt over temp. %/ c 0.01 self - test output change on activation g 0.35 0.5 0.65 mechanical resonance ( - 3db) 3 hz 3500 (xy) 1800 (z) non - linearity % of fs 0.6 cross axis sensitivity % 2 noise (rms at 50hz with low - pass filter = odr/9 ) 4 mg 0.7 5 table 1 : mechanical specifications notes: 1. resolution and acceleration ranges are user selectable via i 2 c or spi . 2. s ensitivity is proportion al to bres in buf_cntrl2. 3. resonance as defined by the dampened mechanical sensor. 4. noise varies with output data rate (odr) and current consumption settings. contact kionix engineering for additional details on fl exset? performance optimization.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 7 of 75 electrical ( specifications are for operation at vdd = 2.5 v and t = 25 c unless stated otherwise) parameters uni ts min typical max supply voltage ( vdd ) operating v 1.71 2.5 3.6 i/o pads supply voltage ( io_vdd ) v 1.7 vdd current consumption high resolution mode (res = 1) ? a 1 45 low power mode 1 (res = 0) 10 standby 0.9 output low v oltage ( io_vdd < 2v) 2 v - - 0.2 * io_vdd output low voltage ( io_vdd 2v) 2 v - - 0.4 output high voltage v 0.8 * io_vdd - - input low voltage v - - 0.2 * io_vdd input high voltage v 0.8 * io_vdd - - input pull - down current ? a 0 start up time 3 ms 2.0 650 power up time 4 ms 10 i 2 c communication rate mhz 3.4 spi communication rate mhz 10 output data rate (odr) 5 hz 0.781 50 1600 bandwidth ( - 3db) 6 res = 0 hz 800 res = 1 hz odr/2 table 2 : electrical specifications notes: 1. current varies with output data rate ( odr ) as shown the chart below, and with noise level settings. contact kionix engineering for additional details on fl exset? performance optimization . 2. for i 2 c communication, this assumes a minimu m 1.5 k ? pull - up resistor on scl and sda pins. 3. startup time is from pc1 set to valid outputs. time varies with output data rate (odr); see chart below 4. power up time is from vdd valid to device boot completion. 5. user selectable through i 2 c or spi . 6. user selec table and de pende nt on odr and res.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 8 of 75 start up time profile current profile odr (hz) time (ms) 1600 3.0 800 3.0 400 4.4 200 7.0 100 12 50 22 25 40 12.5 81 kx022 start up time 3.0 3 4.4 7.0 12 22 40 81 1.0 10.0 100.0 1 10 100 1000 10000 start up time (ms) odr (hz) kx022 start up time (ms) odr (hz) res current ( a) 0 standby 0.9 0.781 0 1.8 1.563 0 2.0 3.125 0 2.2 6.25 0 3.0 12.5 0 5 25 0 7 50 0 13 100 0 21 200 0 43 400 1 146 800 1 146 1600 1 146 representative current profile 1.8 2.0 2.2 3.0 5 7 13 21 43 146 146 146 1.0 10.0 100.0 1000.0 0.1 1 10 100 1000 10000 current ( a) accelerometer odr (hz) representative current (a) 16x averaging filter (default ) res = 0 res = 1 when odr 400hz
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 9 of 75 power - on procedure proper functioning of power - on reset (por) is dependent on the specific vdd, vdd low , t vdd (rise time) , and t vdd _ off profile of individual application s. it is recommended to minimize vdd low, and t vdd , and maximize t vdd_off . it is also advised that the vdd ramp up time t vdd be monotonic. note that the outputs will not be stable until vdd has reached its final value. to assure proper por, the applicat ion should be evaluated over the customer specified range of vdd, vdd low , t vdd , t vdd_off and temperature as por performance can vary depending on these parameters. please refer to technical note tn0 1 4 kx 022, k x 0 23 accelerometer power - on procedure for mor e information.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 10 of 75 environmental parameters units min typical max supply voltage ( vdd ) absolute limits v - 0.5 - 3. 63 operating temperature range c - 40 - 85 storage temperature range c - 55 - 150 mech. shock (powered and unpowered) g - - 5000 for 0.5ms 10000 for 0.2ms esd hbm v - - 2000 table 3 : environmental specifications caution: esd sensitive and mechanical shock sensitive component, improper handling can cause permanent damage to the device. t hese product s conform to rohs directive 2011/65/eu of the european parliament and of the council of the european union that was issued june 8, 2011. specifical ly, these product s do not contain any non - exempted amounts of lead, mercury, cadmium, hexavalent chromium, p olybrominated biphenyls (pbb) or polybrominated diphenyl ethers (pbde) above the maximum concentration values (mcv) by weight in any of its homogenous materials. homogenous materials are of uniform composition throughout. the mcv for lead, mercury, hex avalent chromium, pbb, and pbde is 0.10%. the mcv for cadmium is 0.010%. applicable exemption: 7c - i - electrical and electronic components containing lead in a glass or ceramic other than dielectric ceramic in capacitors (piezoelectronic devices) or in a glass or ceramic matrix compound. these products are also in conformance with reach regulation no 1907/2006 of the european parliament and of the council that was issued dec. 30, 2011. they do not contain any substances of very high concern (svhc - 161) as identified by the european chemicals agency as of 17 december 2014. this product is halogen - free per iec 61249 - 2 - 21. specifically, the materials used in this product contain a maximum total halogen content of 1500 ppm with less than 900 - ppm bromin e and less than 900 - ppm chlorine. soldering soldering recommendations are available upon request or from www.kionix.com . hf
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 11 of 75 terminology g a unit of acceleration equal to the acceleration of gravity at the earth's su rface. one thousandth of a g (0.0098 m/ s 2 ) is referred to as 1 milli - g (1 mg). sensitivity the sensitivity of an accelerometer is the change in output per unit of input acceleration at nominal vdd and temperature . the term is ess entially the gain of the sensor expressed in counts per g (counts/g) or lsbs per g (lsb/g). occasionally, sensitivity is expressed as a resolution, i.e. milli - g per lsb (mg/lsb) or milli - g per count (mg/count) . sensitivity for a given axis is determined by measurements of the formula: the sensitivity tolerance describes the range of s ensitivities that can be expected from a large population of sensors at room temperature and over life . when the temperature deviates from room tempe rature (25 oc ), the s ensitivity will vary by the amount shown in table 1 . zero - g offset zero - g offset or 0 - g offset describes the actual output of the accelerometer when no acceleration is applied . ideally, t he output would alway s be in the middle of the dynamic range of the sensor (content of the out x, outy, outz registers = 00h, e xpressed as a 2s complement number). however, because of mismatches in the sensor, calibration errors, and mechanical stress, the output can deviate f rom 00h. this deviation from the ideal value is called 0 - g offset. the z ero - g offset tolerance describes the range of 0 - g offsets of a population of sensors over the operating temperature range. self - test self - test allows a functional test of the sensor without applying a physical acceleration to it . when activated, an electrostatic force is applied to the sensor, simulating an i nput acceleration. t he sensor outputs respond accordingly . if the output signals change within the amplitude specified table 1 , then the sensor is working properly and the parameters of the interface chip are within the defined specifications. 2 8 . 9 1 s m g ? ? ? g g output g output y sensitivit 2 1 @ 1 @ ? ? ? ?
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 12 of 75 functionality sense element the sense element is fabricated using kionixs proprietary plasma micromachining process technology. th is process technology allows kionix to create mechanical silicon structures which are essentially mass - spring systems that move in the direction of the appli ed acceleration. acceleration sensing is based on the principle of a differe ntial capacitance arising from the acceleration - ind uced motion . capacitive plates on the moving mass move relative to fixed capacitive plates anchored to the substrate . the sense element is hermetically sealed at the wafer level by bonding a second silico n lid wafer to the device using a glass frit. as ic interface a separate asic device packaged with the sense element provides all of the signal conditioning and communication with the sensor . the complete measurement chain is com posed by a low - noise capa citance to voltage amplifier which converts the differential capacitance of the mems sensor into an analog voltage that is sent through an analog - to - digital converter. the acceleration data may be accessed through the i 2 c digital communications provided by the asic. in addition, the asic contains all of the logic to allow the user to choose data rates, g - ranges, filter settings, and interrupt logic. plus, there are two programmable state machines which allow the user to create unique embedded functions ba sed on changes in acceleration. factory calibration kionix trims the offset and sensitivity of each accelerometer by adjusting gain (sensitivity) and 0 - g offset trim codes stored in nonvolatile memory (otp). additionally, all functional register default values are also programmed into the nonvolatile memory . every time the device is turned on or a software reset command is issued , the trimming parameters and default register values are downloaded into the volatile registers to be used during active opera tion. this allows the device to function without further calibration.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 13 of 75 application schematic pin descriptions pin name description 1 sdo/addr serial data out pin during 4 wire spi communication and part of the device address during i2c communicati on. 2 sdi/ sda spi data input / i2c serial data 3 io vdd the power supply input for the digital communication bus. optionally decouple this pin to ground with a 0.1uf ceramic capaci tor. 4 trig trigger pin for fifo buffer control C connect to gnd when no t using external trigger option 5 int1 physical interrupt 1 6 int2 physical interrupt 2 7 vdd the power supply input. decouple this pin to ground with a 0.1uf ceramic capacitor. 8 gnd ground 9 gnd ground 10 ncs spi enable / i2c mode select (0 = spi enabled, i2c communication disabled / 1 = spi disabled, i2c communication enabled) 11 nc not internally connected C can be connected to vdd , io vdd, gnd or float 12 sclk/scl spi and i 2 c serial clock table 4 : pin description s 1 12 11 10 2 9 3 8 4 5 6 7 sdo/addr sdi/sda io_vdd trig int1 int2 vdd gnd ncs scl c 1 c 2
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 14 of 75 test specifications ! special characteristics : these characteristics have been identified as being critical to the customer. every part is tested to verify its conformance to specification prior to shipment. parameter specification test conditions zero - g offset @ rt 1 (2g range) 0 1475 counts 25 c, vdd = 2.5 v sensitivity @ rt 1 (2g range) 16384 983 counts/g 25 c, vdd = 2.5 v table 5 : test specifications 1 room temperature = 25 c
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 15 of 75 package dimensions and orienta tion dimensions 2 x 2 x 0.9 mm lga all dimensions and tolerances conform to asme y14.5m - 1994
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 16 of 75 orientation when device is accelerated in +x, +y or +z direction, the corresponding output will increase. static x/y/z output response versus orientation to earths surface (1g): gsel1=0, gsel0=0 ( 2g) position 1 2 3 4 5 6 diagram top bottom bottom top resolution (bits) 1 6 8 1 6 8 1 6 8 1 6 8 1 6 8 1 6 8 x (counts) 16384 64 0 0 - 16384 - 64 0 0 0 0 0 0 y (counts) 0 0 - 16384 0 - 64 0 0 16384 64 0 0 0 0 z (counts) 0 0 0 0 0 0 0 0 0 16384 64 - 16384 - 64 x - polarity + 0 - 0 0 0 y - polarity 0 - 0 + 0 0 z - polarity 0 0 0 0 + - (1g) earths surface pin 1 +x +y +z
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 17 of 75 static x/y/z output respons e versus orientation to earths surface (1g): gsel1=0, gsel0=1 ( 4g) position 1 2 3 4 5 6 diagram top bottom bottom top resolution (bits) 16 8 16 8 16 8 16 8 16 8 16 8 x (counts) 8192 32 0 0 - 8192 - 32 0 0 0 0 0 0 y (co unts) 0 0 - 8192 - 32 0 0 8192 32 0 0 0 0 z (counts) 0 0 0 0 0 0 0 0 0 8192 32 - 8192 - 32 x - polarity + 0 - 0 0 0 y - polarity 0 - 0 + 0 0 z - polarity 0 0 0 0 + - (1g) earths surface static x/y/z output response versus orientation to earths surface (1g): gsel1=1, gsel0=0 ( 8g) position 1 2 3 4 5 6 diagram top bottom bottom top resolution (bits) 16 8 16 8 16 8 16 8 16 8 16 8 x (counts) 4096 16 0 0 - 4096 - 16 0 0 0 0 0 0 y (cou nts) 0 0 - 4096 - 16 0 0 4096 16 0 0 0 0 z (counts) 0 0 0 0 0 0 0 0 0 409 6 16 - 4096 - 16 x - polarity + 0 - 0 0 0 y - polarity 0 - 0 + 0 0 z - polarity 0 0 0 0 + - (1g) earths surface
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 18 of 75 digital interface the kionix kx022 digital ac celerometer has the ability to communicate via the i 2 c and spi digital serial interface protocols . this a llows for easy system integration by eliminating analog - to - digital converter requirements and by providing direct communication with system micro - cont rollers . the serial interface terms and descriptions as indicated in table 6 below will be observed throughout this document. term description transmitter the device that transmits data to the bus. receiver the device that re ceives data from the bus. master the device that initiates a transfer, generates clock signals, and terminates a transfer. slave the device addressed by the master. table 6 : serial interface terminologies i 2 c serial interface as previously mentioned, the kx022 has the ability to communicate on an i 2 c bus. i 2 c is primarily used for synchronous serial communication between a master device and one or more slave devices. the master, typically a micro controller, provides the ser ial clock signal and addresses slave devices on the bus. the kx022 always operates as a slave device during standard master - slave i 2 c operation. i 2 c is a two - wire serial interface that contains a serial clock (scl) line and a serial data (sda) line. scl is a serial clock that is provided by the master, but can be held low by any slave device, putting the master into a wait condition. sda is a bi - directional line used to transmit and receive data to and from the interface. data is transmitted msb (most significant bit) first in 8 - bit per byte format, and the number of bytes transmitted per transfer is unlimited. the i 2 c bus is considered free when both lines are high. the i2c interface is compliant with high - speed mode, fast mode and standard mode i2 c protocols.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 19 of 75 figure 1 : multiple kx022 i 2 c connection i2c address description address pad 7 bit address address <7> <6> <5> <4> <3> <2> <1> <0> i2c wr io_ vdd 1 fh 3 eh 0 0 1 1 1 1 1 0 i2c rd io_ vdd 1 fh 3 fh 0 0 1 1 1 1 1 1 i2c wr vss 1 eh 3 ch 0 0 1 1 1 1 0 0 i2c rd vss 1 eh 3 dh 0 0 1 1 1 1 0 1 i 2 c operation transactions on the i 2 c bus begin after the master transmits a start condition (s), which is defined as a high - to - low transition on the data line wh ile the scl line is held high. the bus is considered busy after this condition. the next byte of data transmitted after the start condition contains the slave address (sad) in the seven msbs (most significant bits), and the lsb (least significant bit) te lls whether the master will be receiving data 1 from the slave or transmitting data 0 to the slave. when a slave address is sent, each device on the bus compares the seven msbs with its internally stored address. if they match, the device considers i tself addressed by the master. the kx022s slave address is comprised of a programmable part and a fixed part, which allows for connection of multiple kx022s to the same i 2 c bus. the slave address associated with the kx022 is 001 111x, where the programm able bit, x, is determined by the assignment of addr (pin 1 ) to gnd or io_v dd . figure 1 above shows how two kx022s would be implemented on an i 2 c bus. m cu kx022 sda scl addr sda sl addr scl kx022 io_vdd vss
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 20 of 75 it is mandatory that receiving devices acknowledge (ack) ea ch transaction. therefore, the transmitter must release the sda line during this ack pulse. the receiver then pulls the data line low so that it remains stable low during the high period of the ack clock pulse. a receiver that has been addressed, whethe r it is master or slave, is obliged to generate an ack after each byte of data has been received. to conclude a transaction, the master must transmit a stop condition (p) by transitioning the sda line from low to high while scl is high. the i 2 c bus is no w free. note that if the kx022 is accessed through i 2 c protocol before the startup is finished a nack signal is sent. writing to 8 - bit register upon power up, the master must write to the kx022s control registers to set its operational mode. therefore, when writing to a control register on the i 2 c bus, as shown sequence 1 on the following page, the following protocol must be observed: after a start condition, sad+w transmission, and the kx022 ack has been returned, an 8 - bit register address (ra) comman d is transmitted by the master. this command is telling the kx022 to which 8 - bit register the master will be writing the data. since this is i 2 c mode, the msb of the ra command should always be zero (0). the kx022 acknowledges the ra and the master tran smits the data to be stored in the 8 - bit register. the kx022 acknowledges that it has received the data and the master transmits a stop condition (p) to end the data transfer. the data sent to the kx022 is now stored in the appropriate register. the kx0 22 automatically increments the received ra commands and, therefore, multiple bytes of data can be written to sequential registers after each slave ack as shown in sequence 2 on the following page. note** if a stop condition is sent on the least significa nt bit of write data or the following master acknowledge cycle, the last write operation is not guaranteed and it may alter the content of the affected registers . reading from 8 - bit register when reading data from a kx022 8 - bit register on the i 2 c bus, a s shown in sequence 3 on the next page, the following protocol must be observed: the master first transmits a start condition (s) and the appropriate slave address (sad) with the lsb set at 0 to write. the kx022 acknowledges and the master transmits th e 8 - bit ra of the register it wants to read. the kx022 again acknowledges, and the master transmits a repeated start condition (sr). after the repeated start condition, the master addresses the kx022 with a 1 in the lsb (sad+r) to read from the previou sly selected register. the slave then acknowledges and transmits the data from the requested register. the master does not acknowledge (nack) it received the transmitted data, but transmits a stop condition to end the data transfer. note that the kx022 automatically increments through its sequential registers, allowing data to be read from multiple registers following a single sad+r command as shown below in sequence 4 on the following page. reading data from a buffer read register is a special case beca use if register address (ra) is set to buffer read register (buf_read) in sequence 4, the register auto - increment feature is automatically disabled. instead, the read pointer will increment to the next data in the buffer, thus allowing reading multiple byt es of data from the buffer using a single sad+r command.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 21 of 75 data transfer sequences the following information clearly illustrates the variety of data transfers that can occur on the i 2 c bus and how the master and slave interact during these transfers. table 7 defines the i 2 c terms used during the data transfers. term definition s start condition sr repeated start condition sad slave address w write bit r read bit ack acknowledge nack not acknowledge ra register addres s data transmitted/received data p stop condition table 7 : i 2 c terms sequence 1. the master is writing one byte to the slave. master s sad + w ra data p slave ack ack ack sequence 2 . the master is writing multiple bytes to the slave. master s sad + w ra data data p slave ack ack ack ack sequence 3. the master is receiving one byte of data from the slave. master s sad + w ra sr sad + r nack p slave ack ack ack dat a sequence 4. the master is receiving multiple bytes of data from the slave. master s sad + w ra sr sad + r ack nack p slave ack ack ack data data
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 22 of 75 hs - mode to enter the 3.4mhz high speed mode of communication, the dev ice must receive the following sequence of conditions from the master: a start condition followed by a master code (00001xxx) and a master non - acknowledge. once recognized, the device switches to hs - mode communication. read/write data transfers then pro ceed as described in the sequences above. devices return to the fs - mode after a stop occurrence on the bus. sequence 5 . hs - mode data transfer of the master writing multiple byte s to the slave. speed fs - mode hs - mode fs - mode master s m - code nack s r sad + w ra data p slave ack ack ack sequence 6 . hs - mode data transfer of the master receiving multiple byte s of data from the slave. speed fs - mode hs - mode master s m - code nack s r sad + w ra slave ack ack speed hs - mode fs - mode master s r sad + r nack p slave ack data ack data n bytes + ack. (n - 1) bytes + ack.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 23 of 75 i 2 c timing diagram table 8 : i 2 c timing (fast mode) number description min max units t 0 sda low to scl low transition (start event) 50 - ns t 1 sda low to first scl rising edge 100 - ns t 2 scl pulse width: high 100 - ns t 3 scl pulse width: low 100 - ns t 4 scl high before sda falling edge (start repeated) 50 - ns t 5 scl pulse width: high during a s/sr/p event 100 - ns t 6 scl high b efore sda rising edge (stop) 50 - ns t 7 sda pulse width: high 25 - ns t 8 sda valid to scl rising edge 50 - ns t 9 scl rising edge to sda invalid 50 - ns t 10 scl falling edge to sda valid (when slave is transmitting) - 100 ns t 11 scl falling edge t o sda invalid (when slave is transmitting) 0 - ns note recommended i 2 c clk 2.5 - us
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 24 of 75 spi communications 4 - wire spi interface the kx022 also utilizes an integrated 4 - wire serial peripheral interface (spi) for digital communication. the spi interf ace is primarily used for synchronous serial communication between one master device and one or more slave devices. the master, typically a micro controller, provides the spi clock signal (sclk) and determines the state of chip select (ncs). the kx022 al ways operates as a slave device during standard master - slave spi operation. 4 - wire spi is a synchronous serial interface that uses two control and two data lines. with respect to the master, the serial clock output (sclk), the data output (sdi or mosi) a nd the data input (sdo or miso) are shared among the slave devices. the master generates an independent chip select (ncs) for each slave device that goes low at the start of transmission and goes back high at the end. the slave data output (sdo) line, re mains in a high - impedance (hi - z) state when the device is not selected, so it does not interfere with any active devices. this allows multiple slave devices to share a master spi port as shown in figure 2 below. figure 2 : 4 - wire spi connections
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 25 of 75 4 - wire spi timing diagram table 9 : 4 - wire spi timing number description min max units t 1 clk pulse width: high 40 ns t 2 clk pulse width: low 40 ns t 3 ncs low to first clk rising edge 20 ns t 4 ncs low after the final clk rising edge 30 ns t 5 sdi valid to clk rising edge 10 ns t 6 clk rising edge to sdi invalid 10 ns t 7 clk falling edge to sdo valid 35 ns notes 1. t 7 is only present durin g reads. 2. timings are for vdd of 1.8v to 3.6v with 1k ? pull - up resistor and maximum 20pf load capacitor on sdo. t sdo sdi ncs t 3 clk bit 7 bit 6 bit 1 5 bit 0 bit 7 5 bit 6 bit 1 5 bit 0 bit 7 5 bit 6 bit 1 5 bit 0 t 1 t 2 t 4 t 5 t 6 t 7
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 26 of 75 4 - wire read and write registers the registers embedded in the kx022 have 8 - bit addresses. upon power up, the master must write to the acceler ometers control registers to set its operational mode. on the falling edge of ncs , a 2 - byte command is written to the appropriate control register. the first byte initiates the write to the appropriate register, and is followed by the user - defined, data byte. the msb (most significant bit) of the register address byte will indicate 0 when writing to the register and 1 when reading from the register. this operation occurs over 16 clock cycles. all commands are sent msb first. the host must return n cs high for at least one clock cycle before the next data request. however, when data is being read from a buffer read register (buf_read), the ncs signal can remain low until the buffer is read. figure 3 below shows the timing d iagram for carrying out an 8 - bit register write operation. figure 3 : timing diagram for 8 - bit register write operation in order to read an 8 - bit register, an 8 - bit register address must be written to the accelerometer to initiate the read. the msb of this register address byte will indicate 0 when writing to the register and 1 when reading from the register. upon receiving the address, the accelerometer returns the 8 - bit data stored in the add ressed register. this operation also occurs over 16 clock cycles. all returned data is sent msb first, and the host must return ncs high for at least one clock cycle before the next data request. figure 4 shows the timing diag ram for an 8 - bit register read operation. figure 4 : timing diagram for 8 - bit register read operation a7 a6 a5 a4 a3 a2 a1 a0 sdo sdi clk cs d2 d1 write addr ess first 8 bits hi - z hi - z d7 d6 d5 second 8 bits last 8 bits hi - z d0 d7 d6 d5 d4 d3 d2 d1 d0 sdo sdi clk cs d2 d1 d5 d6 d7 a7 a6 a5 a4 a3 a2 a1 a0 read a ddress hi - z first 8 bits hi - z d2 d3 d4 d7 d0 d1 d6 d 5 last 8 bits hi - z d0 d 3 second 8 bits
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 27 of 75 3 - wire spi interface the kx022 also utilizes an integrated 3 - wire serial peripheral interface (spi) for digital communication. 3 - wire spi is a synchronous serial interface that uses two control lines and one data line. with respect to the master, the serial clock output (sclk), the data output/input (sdi) are shared among the slave devices. the master generates an independent chip select (ncs) for each slave device that goes low at the start of transmission and goes back high at the end. this allows multiple slave devices to share a master spi port as shown in figure 5 below. figure 5 : 3 - wire spi connections
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 28 of 75 3 - wire spi timing diagram table 10 . 3 - wire spi timing number description min max units t 1 clk pulse width: high 40 - ns t 2 clk pulse width: low 40 - ns t 3 ncs low to first clk rising edge 20 - ns t 4 ncs low after the final clk falling edge 20 - ns t 5 sdi valid to clk rising edge 10 - ns t 6 clk rising edge to sdi input invalid 10 - ns t 7 clk extra clock cycle rising edge t o sdi output becomes valid - - ns t 8 clk falling edge to sdi output becomes valid - 35 ns notes 1. t 7 and t 8 are only present during reads. 2. timings are for vdd of 1.8v to 3.6v with 1k ? pull - up resistor and maximum 20pf load capacitor on sdi. sdi ncs t 3 clk bit 7 bit 6 bit 1 5 bit 0 bit 7 bit 1 5 bit 0 t 1 t 2 t 7 t 4 t 5 t 6 t 8
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 29 of 75 3 - wire rea d and write registers the registers embedded in the kx022 have 8 - bit addresses. upon power up, the master must write to the accelerometers control registers to set its operational mode. on the falling edge of ncs , a 2 - byte command is written to the app ropriate control register. the first byte initiates the write to the appropriate register, and is followed by the user - defined, data byte. the msb (most significant bit) of the register address byte will indicate 0 when writing to the register and 1 when reading from the register. a read operation occurs over 17 clock cycles and a write operation occurs over 16 clock cycles. all commands are sent msb first. the host must return ncs high for at least one clock cycle before the next data request. howe ver, when data is being read from a buffer read register (buf_read), the ncs signal can remain low until the buffer is read. figure 6 below shows the timing diagram for carrying out an 8 - bit register write operation. figure 6 : timing diagram for 8 - bit register write operation in order to read an 8 - bit register, an 8 - bit register address must be written to the accelerometer to initiate the read. the msb of this register addr ess byte will indicate 0 when writing to the register and 1 when reading from the register. upon receiving the address, the accelerometer returns the 8 - bit data stored in the addressed register. for 3 - wire read operations, one extra clock cycle betwe en the address byte and the data output byte is required. therefore, this operation occurs over 17 clock cycles. all returned data is sent msb first, and the host must return ncs high for at least one clock cycle before the next data request. figure 7 shows the timing diagram for an 8 - bit register read operation. figure 7 : timing diagram for 8 - bit register read operation a7 a6 a5 a4 a3 a2 a1 a0 sdi sclk cs d7 d6 d5 d4 d3 d2 d1 d0 (msb) (msb) a7 a6 a5 a4 a3 a2 a1 a0 sdi sclk cs d7 d6 d5 d4 d3 d2 d1 d0 hi - z (msb) (msb)
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 30 of 75 embedded registers the kx022 has 57 embedded 8 - bi t registers that are accessible by the user. this section contains the addresses for all embedded registers and also describes bit functions of each register. table 11 below provides a listing of the accessible 8 - bit registers and their addresses. address register name r/w address register name r/w 00h xhpl r 21h inc6* r/w 01h xhph r 22h tilt_timer* r/w 02h yhpl r 23h wufc* r/w 03h yhph r 24h tdtrc* r/w 04h zhpl r 25h tdtc* r/w 05h zhph r 26h tth* r/w 06h xoutl r 27h ttl* r/w 07h xouth r 28h ftd* r/w 08h youtl r 29h std* r/w 09h youth r 2ah tlt* r/w 0ah zoutl r 2bh tws* r/w 0bh zouth r 2ch kionix reserved 0ch cotr r 2dh kionix reserved 0dh kionix reserved 2eh kionix reserved 0eh kionix reserved 2fh kionix reserved 0fh who_am_i r/w 30h ath* r/w 10h tscp r 31h kionix reserved 11h tspp r 32h tilt_angle_ll* r/w 12h ins1 r 33h tilt_angle_hl* r/w 13h ins2 r 34h hyst_set* r/w 14h ins3 r 35h lp_cntl* r/w 15h stat r 36h kionix reserve d 16h kionix reserved 37h kionix reserved 17h int_rel r 38h kionix reserved 18h cntl1* r/w 39h kionix reserved 19h cntl2* r/w 3ah buf_cntl1* r/w 1ah cntl3* r/w 3bh buf_cntl2* r/w 1bh odcntl* r/w 3ch buf_status_1 r 1ch inc1* r/w 3dh buf_status_2 r 1dh inc2* r/w 3eh buf_clear w 1eh inc3* r/w 3fh buf_read r 1fh inc4* r/w 60h self_test r/w 20h inc5* r/w * note: - when changing the contents of these registers, the pc1 bit in ctrl_reg1 must first be set to 0. - rese rved registers should not be written. table 11 : register map
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 31 of 75 register descriptions accelerometer outputs these registers contain up to 1 6 - bits of valid acceleration data for each axis . depending on the setting of the res bit in ctrl_reg1, the user may choose to read only the 8 msb thus reading an effective 8 - bit resolution. when bres = 0 in buf_cntl2 the 8 msb is the only data recorded in the buffer. the data is updated every user - defined odr period, is protected from overwrite during each read, and can be converted from digital counts to acceleration (g) per 12 below. the register acceleration output binary data is represented in 2s complemen t format. for example, if n = 16 bits, then the counts range is from - 32768 to 32767 , a nd if n = 8 bits, then the counts range is from - 128 to 127. 16 - bit register data (2s complement) equivalent counts in decimal range = 2g range = 4g range = 8g 0111 1111 1111 1111 32767 +1.99994g +3.99988g +7.99976g 0111 1111 1111 1110 32766 +1. 99988g +3.99976g +7.99951g 0000 0000 0001 1 +0.00006g +0.00012g +0.00024g 0000 0000 0000 0 0.000g 0.0000g 0.0000g 1111 1111 1111 1111 - 1 - 0.00006g - 0.00012g - 0.00024g 1000 0000 0000 0001 - 32767 - 1.99994g - 3.99988g - 7.99976g 1000 0000 0000 0000 - 32768 - 2.00000g - 4.00000g - 8.00000g 8 - bit register data (2s complement) equivalent counts in decimal range = 2g range = 4g range = 8g 0111 1111 127 +1.9844g +3.9688g +7.9375g 0111 1110 126 +1.9688g +3.9375g +7.8750g 0000 0001 1 +0.0156g +0.0313g +0.0625g 0000 0000 0 0.0000g 0.0000g 0.0000g 1111 1111 - 1 - 0.0156g - 0.0313g - 0.0625g 1000 0001 - 127 - 1.9844g - 3.9688g - 7.9375g 1000 0000 - 128 - 2.000g - 4.000g - 8.000g table 12 : acceler ation (g) calculation
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 32 of 75 xhp_l x - axis high pass filter accelerometer output least significant byte . data is updated at the odr frequency determined by owuf in cntl3 . r r r r r r r r xhpd7 xhpd6 xhpd5 xhpd4 xhpd3 xhpd2 xhpd1 xhpd0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x00h xhp_h x - axis high pass filter accelerometer output most significant byte . data is updated at the odr frequency determined by owuf in cntl3 . r r r r r r r r xhpd15 xhpd14 xhpd13 xhpd12 xhpd11 xhpd10 xhpd9 xhp d8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x01h yhp_l y - axis high pass filter accelerometer output least significant byte . data is updated at the odr frequency determined by owuf in cntl3 . r r r r r r r r yhpd7 yhpd6 yhpd5 yhpd 4 yhpd3 yhpd2 yhpd1 yhpd0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x02h yhp_h y - axis high pass filter accelerometer output most significant byte . data is updated at the odr frequency determined by owuf in cntl3 . r r r r r r r r yhpd15 yhpd14 yhpd13 yhpd12 yhpd11 yhpd10 yhpd9 yhpd8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x03h
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 33 of 75 zhp_l z - axis high pass filter accelerometer output least significant byte . data is updated at the odr frequency determined by owuf in cntl3 r r r r r r r r zhpd7 zhpd6 zhpd5 zhpd4 zhpd3 zhpd2 zhpd1 zhpd0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x04h zhp_h z - axis high pass filter accelerometer output most significant byte . data is updated at the odr freque ncy determined by owuf in cntl3 . r r r r r r r r zhpd15 zhpd14 zhpd13 zhpd12 zhpd11 zhpd10 zhpd9 zhpd8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x05h xout_l x - axis accelerometer output least significant byte . data is updated at the odr frequency determined by osa in odcntl . r r r r r r r r xoutd 7 xoutd 6 xoutd 5 xoutd 4 xoutd3 xoutd2 xoutd1 xoutd0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x06h xout_h x - axis accelerometer output most significant byte . dat a is updated at the odr frequency determined by osa in odcntl. r r r r r r r r xoutd1 5 xoutd1 4 xoutd 13 xoutd 12 xoutd 11 xoutd 10 xoutd 9 xoutd 8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x07h
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 34 of 75 yout_l y - axis accelerometer output least significant byte . data is updated at the odr frequency determined by osa in odcntl. r r r r r r r r youtd7 youtd6 youtd5 youtd4 youtd3 youtd2 youtd1 youtd0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x08h yout_h y - axis accelerome ter output most significant byte . data is updated at the odr frequency determined by osa in odcntl. r r r r r r r r y outd15 y outd14 y outd13 y outd12 y outd11 y outd10 y outd9 y outd8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x09h zou t_l z - axis accelerometer output least significant byte . data is updated at the odr frequency determined by osa in odcntl. r r r r r r r r zoutd7 zoutd6 zoutd5 zoutd4 zoutd3 zoutd2 zoutd1 zoutd0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x0ah zout_h z - axis accelerometer output most significant byte . data is updated at the odr frequency determined by osa in odcntl. r r r r r r r r y outd15 y outd14 y outd13 y outd12 y outd11 y outd10 y outd9 y outd8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x0bh
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 35 of 75 cotr this register can be used to verify proper integrated circuit functionality. it always has a byte value of 0x55h unless the cotc bit in cntl2 is set. at that point this value is set to 0xaah. the byte value is retur ned to 0x55h after reading this register and the cotc bit in cntl2 is cleared . r r r r r r r r dcstr7 dcstr6 dcstr5 dcstr4 dcstr3 dcstr2 dcstr1 dcstr0 reset value 7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01010101 i 2 c address: 0x0ch who_am_i this register can be used for supplier recognition, as it can be factory written to a known byte value. the default value is 0x 14 h . r r r r r r r r wia7 wia6 wia5 wia4 wia3 wia2 wia1 wia0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00010100 i 2 c address: 0x0fh tilt position registers these two registers report previous and current position data that is updated at the user - defined odr frequency and is protected during register read. table 13 describes the reported position for each bit value. tscp current tilt position register. r r r r r r r r 0 0 le ri do up fd fu reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00 10000 0 i 2 c address: 0x10h
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 36 of 75 tspp previous tilt posi ton register. r r r r r r r r 0 0 le ri do up fd fu reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00 10000 0 i 2 c address: 0x11h bit description le left state (x - ) ri right state (x+) do down state (y - ) up up state (y+) fd face - dow n state (z - ) fu face - up state (z+) table 13 : tilt position interrupt source registers these t hree registers report interrupt state changes. this data is updated when a new interrupt event occurs and each app lications result is latched until the interrupt release register is read. in s 1 this register indicates the triggering axis when a tap/double tap interrupt occurs. data is updated at the odr settings determined by otdt <2:0> in cntl3 . r r r r r r r r 0 0 tle tri tdo tup tfd tfu bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x12 h bit description tle x negative (x - ) reported tri x positive (x+) reported tdo y negative (y - ) reported tup y positive (y+) reported tfd z negativ e (z - ) reported tfu z positive (z+) reported table 14 . directional tap tm reporting
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 37 of 75 in s 2 this r egister tells w h ich function caused an interrupt. r r r r r r r r 0 bfi wmi drdy tdts1 tdts0 wufs tps bit7 bit6 bit 5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x1 3 h bfi C indicates buffer full interrupt. automatically cleared when buffer is read. bfi = 0 C buffer is not full bfi = 1 C buffer is full wmi C watermark interrupt, bit is set to one when fifo h as filled up to the value stored in the sample bits. this bit is automatically cleared when fifo/filo is read and the content returns to a value below the value stored in the sample bits. wmi = 0 C buffer watermark has not been exceeded wmi = 1 C buffer w atermark has been exceeded drdy C indicates that new acceler ation data ( 0x 06h to 0x 0bh) is available. this bit is cleared when acceleration data is read or the inter rupt release register int_rel is read. drdy = 0 - new a cceleration data not available dr dy = 1 - new acceleration data available tdts(1,0) C status of tap/double tap, bit is released when interrupt release register int_rel is read. tdts1 tdts0 event 0 0 no tap 0 1 single tap 1 0 double tap 1 1 do not exist wufs C status of wake up . thi s bit is cleared when the interrupt release register int_rel is read . wufs = 1 C motion has activated the interrupt wufs = 0 C no motion tps C tilt position status. this bit is cleared when the interrupt release register int_rel is read . tps = 0 C positi on not changed tps = 1 C position changed
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 38 of 75 ins3 this register reports the axis and direction of detected motion. r r r r r r r r 0 0 xnwu xpwu ynwu ypwu znwu zpwu bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x14 h bit description xnwu x negative (x - ) reported xpwu x positive (x+) reported ynwu y negative (y - ) reported ypwu y positive (y+) reported znwu z negative (z - ) reported zpwu z positive (z+) reported table 15 : motion detection t m reporting status_reg this register reports the status of the interrupt. r r r r r r r r 0 0 0 int 0 0 0 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x15 h int reports the combined (or) interrupt information of all features. w hen bfi and wmi in ins2 are 0, the int bit is released to 0 when int_rel is read. if wmi or bfi is 1, int bit remains at 1 until they are cleared by fifo/filo buffer read. 0 = no interrupt event 1 = interrupt event has occurred int_rel latched interru pt source information (ins1 , ins2 , ins3 except wmi/bfi and int when wmi/bfi is zero) is cleared and physical interrupt latched pin is changed to it s inactive state when this register is read. read value is dummy. r r r r r r r r x x x x x x x x bit7 bit 6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x17 h
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 39 of 75 cntl1 read/write control register that controls the main feature set. r/w r/w r/w r/w r/w r/w r/w r/w pc1 res drdye gsel1 gsel0 tdte wufe tpe reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000 i 2 c address: 0x18 h pc1 controls the operating mode of the kx022 . when in res = 0, please allow 1.2/odr delay time when transitioning from stand - by pc1 = 0 to operating mode pc1 = 1 to allow new settings to load. 0 = stand - by mod e 1 = operating mode res determines the performance mode of the kx022 . the noise varies with odr , res and different lp_cntl settings possibly reducing the effective resolution. note that to change the value of this bit, the pc1 bit must first be set to 0. 0 = low current . 1 = high current . bandwidth (hz) = odr/2 drdye enables the reporting of the availability of new acceleration data as an interrupt. note that to change the value of this bit, the pc1 bit must first be set to 0. 0 = availability o f new acceleration data is not reflected as an interrupt 1 = availability of new acceleration data is reflected as an interrupt gsel1, gsel0 selects the acceleration range of the ac celerometer outputs per table 16 . note that to change the value of this bit, the pc1 bit must first be set to 0 . gsel1 gsel0 range 0 0 2g 0 1 4g 1 0 8g table 16 : selected acceleration range tdte enables the directional tap tm function that will dete ct single and double tap events. note that to change the value of this bit, the pc1 bit must first be set to 0. tdte = 0 C disable tdte = 1 - enable
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 40 of 75 wuf e enables the wake up (motion detect) function. 0= disabled, 1= enabled. note that to change the va lue of this bit, the pc1 bit must first be set to 0. 0 = wake up function disabled 1 = wake up function enabled tpe enables the tilt position function that will detect changes in device orientation. note that to change the value of this bit, the pc1 bi t must first be set to 0. tpe = 0 C disable tpe = 1 C enable cntl2 read/write control register that provides more feature set control. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/ w r/w r/w r/w r/w r/w r/w srst cotc lem rim dom upm fdm fum reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00 111111 i 2 c address: 0x19 h srst initiates software reset, which performs the ram reboot routine. this bit will remain 1 until t he ram reboot routine is finished. srst = 0 C no action srst = 1 C start ram reboot routine cotc command test control. dcst = 0 C no action dcst = 1 C sets st r r egister to 0xaah and when str is read, sets this bit to 0 and sets st r to 0x55h tlem, tr im, tdom, tupm, tfdm these bits control the tilt axis mask. per table 17 , if a directions bit is set to one (1), tilt in that direction will generate an interrupt. if it is set to zero (0), tilt in that directio n will not generate an interrupt. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. bit description tlem x negative (x - ) trim x positive (x+) tdom y negative (y - ) tupm y positive (y+) t fdm z negative (z - ) tfum z positive (z+) table 17 : tilt direction tm axis mask
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 41 of 75 cntl3 read/write control register that provides more feature set control. note that to properly change the value of this register, t he pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w otp1 otp0 otdt2 otdt1 otdt0 owuf2 owuf1 owuf0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1001100 0 i 2 c address: 0x1a h otpa, otpb sets the output da ta rate for the tilt position function per table 18 . the default tilt position odr is 12.5hz. otp1 otp0 output data rate 0 0 1. 5 6 3 hz 0 1 6.25 hz 1 0 12.5hz 1 1 50hz table 18 : tilt position function output data rate otdta, otdtb sets the output data rate for the directional tap tm function per table 19 . the default directional tap tm odr is 400hz. otdt2 otdt1 otdt0 output data rate 0 0 0 50hz 0 0 1 100hz 0 1 0 200hz 0 1 1 400hz 1 0 0 12.5hz 1 0 1 25hz 1 1 0 800hz 1 1 1 1600hz table 19 : directional tap tm function output data rate
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 42 of 75 owuf2 , owuf 1, owuf0 sets the output data ra te for the general motion detection function and the high - pa ss filtered outputs per table 20 . the default motion wake up odr is 0.781 hz. owuf2 owuf1 owuf0 output data rate 0 0 0 0.781hz 0 0 1 1.563hz 0 1 0 3. 125hz 0 1 1 6.250hz 1 0 0 12.5hz 1 0 1 25hz 1 1 0 50hz 1 1 1 100hz table 20 : motion wake up function output data rate
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 43 of 75 odcntl this register is responsible for configuring odr (output data rate) and filter settings. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w iir_bypass lpro reserved reserved osa3 osa2 osa1 osa0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0000001 0 i 2 c address: 0x1b h iir_bypass filter bypass mode iir_bypass = 0 C filtering applied iir_bypass = 1 C filter bypassed lpr o low - pass filter roll off control lpro = 0 C filter corner frequency set to odr/9 lpro = 1 C fi lter corner frequency set to odr/2 osa3, osa2, osa1, osa0 acceleration output data rate . the default odr is 50hz. osa3 osa2 osa1 osa0 output data rate 0 0 0 0 12.5hz * 0 0 0 1 25hz * 0 0 1 0 50hz * 0 0 1 1 100hz * 0 1 0 0 200hz * 0 1 0 1 400hz 0 1 1 0 800hz 0 1 1 1 1600hz 1 0 0 0 0.781hz * 1 0 0 1 1.563hz * 1 0 1 0 3.125hz * 1 0 1 1 6.25hz * table 21 : accelerometer output data rates (odr) * low power mode available, all other data rates will default to hig h resolution mode
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 44 of 75 inc1 this register controls the settings fo r the physical interrupt pin int 1 . note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w reserved re served ien 1 iea 1 iel 1 reserved stpol spi3e reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00010000 i 2 c address: 0x1c h ien enables/disable s the physical interrupt pin ien = 0 C physical interrupt pin is disabled ien = 1 C physical in terrupt pin is enabled iea sets the polarity o f the physical interrupt pin iea = 0 C polarity of the physical interrupt pin i s active low iea = 1 C polarity of the physical interrupt pin is active high iel sets the response o f the physical interru pt pin iel = 0 C the physical interrupt pin latches until it is cleared by reading int_rel iel = 1 C the physical interrupt pin will transmit one pulse with a period of 50 us stpol sets the polarity of self - test stpol = 0 C negative stpol = 1 C positive spi3e sets the 3 - wire spi interface spi3e = 0 C disabled spi3e = 1 C enabled inc2 this register controls which axis and direction of detected motion can cause an interrupt. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w 0 0 xnwue xpwue ynwue ypwue znwue zpwue reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00111111 i 2 c address: 0x1d h xnwu C x negative (x - ) : 0 = disabled, 1 = enabled xpwu C x positive (x+) : 0 = disabled, 1 = enabled ynwu C y negative (y - ) : 0 = disabled, 1 = enabled
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 45 of 75 ypwu C y positive (y+) : 0 = disabled, 1 = enabled znwu C z negative (z - ) : 0 = disabled, 1 = enabled zpwu C z positive (z+) : 0 = disabled, 1 = enabl ed inc3 this register controls which axis and direction of tap/double tap can cause an interrupt. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w 0 0 tlem tri m tdom tupm tfdm tfum reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00111111 i 2 c address: 0x1e h tlem C x negative (x - ) : 0 = disabled, 1 = enabled trim C x positive (x+) : 0 = disabled, 1 = enabled tdom C y negative (y - ) : 0 = disabled, 1 = enabled tupm C y positive (y+) : 0 = disabled, 1 = enabled tfdm C z negative (z - ) : 0 = disabled, 1 = enabled tfum C z positive (z+) : 0 = disabled, 1 = enabled inc4 this register controls routing of an interrupt repo rting to physical interrupt pi n int 1 . note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w 0 bfi1 wmi1 drdyi1 reserved tdti1 wufi1 tpi1 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00 000000 i 2 c address: 0x1f h bfi1 C buffer full interrupt reported on physical interrupt pin int 1 wmi1 - watermark interrupt reported on physical interrupt pin int 1 drdyi1 C data ready interrupt reported on physical interrupt pin int 1 tdti1 - tap/double tap interrupt reported on physical interrupt pin int 1 wufi1 C wake - up (motion detect) interrupt reported on physical interrupt pin int 1 tpi1 C tilt position interrupt reported on physical interrupt pin int 1
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 46 of 75 inc5 this register controls the settings for the physical interrupt pin int 2 . note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w reserved reserved ien2 iea2 iel2 reserved reserved reserved reset value bit7 b it6 bit5 bit4 bit3 bit2 bit1 bit0 00 010000 i 2 c address: 0x20 h ien2 enables/disables the physical interrupt pin ien2 = 0 C physical interrupt pin is disabled ien2 = 1 C physical interrupt pin is enabled iea2 sets the polarity of the phys ical interrupt pin iea2 = 0 C polarity of the physical interrupt pin is active low iea2 = 1 C polarity of the physical interrupt pin is active high iel2 sets the response of the physical interrupt pin iel2 = 0 C the physical interrupt pin latches until it is cleared by reading int_rel iel2 = 1 C the physical interrupt pin will transmit one pulse with a period of 50 us inc6 this register controls routing of interrupt reporting to physical interrupt pin int 2 . note that to properly change the v alue of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w 0 bfi2 wmi2 drdyi2 reserved tdti2 wufi2 tpi2 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00 000000 i 2 c address: 0x2 1 h bfi 2 C buffer full interrupt reported on physical interrupt pin int 2 wmi 2 - watermark interrupt reported on physical interrupt pin int 2 drdyi 2 C data ready interrupt reported on physical interrupt pin int 2 tdti2 - tap/double tap interrupt reported on physical int errupt pin int 2 wufi 2 C wake - up (motion detect) interrupt reported on physical interrupt pin int 2 tpi 2 C tilt position interrupt reported on physical interrupt pin int 2
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 47 of 75 tilt_timer this register is the initial count register for the tilt position state ti mer (0 to 255 counts). every count is calculated as 1/odr delay period, where the odr is user - defined per table 18 . a new state must be valid as many measurement periods before the change is accepted. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w tsc7 tsc6 tsc5 tsc4 tsc3 tsc2 tsc1 tsc0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000 i 2 c address: 0x22h wufc this register is the initial count register for the motion detection timer (0 to 255 counts). every count is calculated as 1/odr delay period, where the odr is user - defined per table 20 . a new st ate must be valid as many measurement periods before the change is accepted. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w wufc7 wufc6 wufc5 wufc4 wufc3 wufc 2 wufc1 wufc0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000 i 2 c address: 0x23h tdtrc this register is responsible for enabling /disabling reporting of tap/double tap. note that to properly change the value of this register, th e pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 dtre stre reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 000000 11 i 2 c address: 0x24 h dtre enables/disables the double tap interrupt dtre = 0 C do not update/trigger interrupts on double tap events dtre = 1 C update interrupts on double tap events stre enables/disables single tap interrupt stre = 0 C do not update/trigger interrupts on single tap events stre = 1 C update interrupts on single tap events
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 48 of 75 tdtc this register contains counter information for the detection of a double tap event. when the directional taptm odr is 400hz or less, every count is calculated as 1/odr delay period. when the directional taptm odr is 800hz, every c ount is calculated as 2/odr delay period. when the directional taptm odr is 1600hz, every count is calculated as 4/odr delay period. the directional taptm odr is user - defined per table 19 . the tdtc counts starts at the beginning of the fist tap and it represents the minimum time separation between the first tap and the second tap in a double tap event. more specifically , the second tap event must end outside of the tdtc. the kionix recommended default value is 0. 3 seconds (0x78h). note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w tdtc7 tdtc6 tdtc5 tdtc4 tdtc3 tdtc2 tdtc1 tdtc0 reset value bit7 bit6 bit5 bit4 bit3 bit2 b it1 bit0 0 1111000 i 2 c address: 0x25 h tth this register represents the 8 - bit jerk high threshold to determine if a tap is detected. though this is an 8 - bit register, the register value is internally multiplied by two in order to set the high threshold. this multiplication results in a range of 0d to 510d with a resolution of two counts. the performance index (pi) is the jerk signal that is expected to be less than this threshold, but greater than the ttl threshold during single and double ta p events. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. the kionix recommended default value is 203 (0xcb h) and the performance index is calculated as: x = x ( current) C x ( previous) y = y ( current) C y ( previous) z = z ( current) C z ( previous) pi = |x| + |y| + |z| equation 1 : performance index r/w r/w r/w r/w r/w r/w r/w r/w tth7 tth6 tth5 tth4 tth3 tth2 tth1 tth0 reset value bit7 bit6 bit5 bit4 bit3 bit 2 bit1 bit0 11001011 i 2 c address: 0x26 h
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 49 of 75 ttl this register represents the 8 - bit (0d C 255d) jerk low threshold to determine if a tap is detected . the performance index (pi) is the jerk signal that is expected to be greater than this threshold a nd less than the tth threshold during single and double tap events. the kionix recommended default value is 26 (0x1ah). note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w ttl7 ttl6 ttl5 ttl4 ttl3 ttl2 ttl1 ttl0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 000 11010 i 2 c address: 0x27 h ftd this register contains counter information for the detection of any tap event. when the directional taptm odr is 400hz or less, every count is calculated as 1/odr delay period. when the directional taptm odr is 800hz, every count is calculated as 2/odr delay period. when the directional taptm odr is 1600hz, every count is calculated as 4/odr delay period. t he directional taptm odr is user - defined per table 19 . in order to ensure that only tap events are detected, these time limits are used. a tap event must be above the performa nce index threshold for at least the low limit (ftdl0 C ftdl2) and no more than the high limit (ftdh0 C ftdh4). the kionix recommended default value for the high limit is 0.05 seconds and for the low limit is 0.005 seconds (0xa2h). note that to properly change the value of this register, t he pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w ftdh4 ftdh3 ftdh2 ftdh1 ftdh0 ftdl2 ftdl1 ftdl0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 10100010 i 2 c address: 0x28 h std this register contain s counter information for the detection of a double tap event. when the directional tap tm odr is 400hz or less, every count is calculated as 1/odr delay period. when the directional tap tm odr is 800hz, every count is calculated as 2/odr delay period. wh en the directional tap tm odr is 1600hz, every count is calculated as 4/odr delay period. the directional tap tm odr is user - defined per table 19 . in order to ensure that only tap events are detected, this time lim it is used. this register sets the total amount of time that the two taps in a double tap event can be above the pi threshold ( ttl ). the kionix recommended default value for std is 0.09 seconds (0x24h). note that to properly change the value of this reg ister, the pc1 bit in ctrl_reg1 must first be set to 0.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 50 of 75 r/w r/w r/w r/w r/w r/w r/w r/w std7 std6 std5 std4 std3 std2 std1 std0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00100100 i 2 c address: 0x29 h tlt this register contains counter information for the detection of a tap event. when the directional tap tm odr is 400hz or less, every count is calculated as 1/odr delay period. when the directional tap tm odr is 800hz, every count is calculated as 2/odr delay period. when the d irectional tap tm odr is 1600hz, every count is calculated as 4/odr delay period. the directional tap tm odr is user - defined per table 19 . in order to ensure that only tap events are detected, this time limit is us ed. this register sets the total amount of time that the tap algorithm will count samples that are above the pi threshold ( ttl ) during a potential tap event. it is used during both single and double tap events. however, reporting of single taps o n the p hysical interrupt pin int1 or int2 will occur at the end of the tws . the kionix recommended default value for tlt is 0.1 seconds (0x28h). note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w tlt7 tlt6 tlt5 tlt4 tlt3 tlt2 tlt1 tlt0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 001010 00 i 2 c address: 0x2a h tws this register contains counter information for the detection of single and double taps. when the directional tap tm odr is 400hz or less, every count is calculated as 1/odr delay period. when the directional tap tm odr is 800hz, every count is calculated as 2/odr delay period. when the directional tap tm odr is 1600hz, every count is calcula ted as 4/odr delay period. the directional tap tm odr is user - defined per table 19 . it defines the time window for the entire tap event, single or double, to occur. reporting of single taps o n the physical interr upt pin int1 or int2 will occur at the end of this tap window. the kionix recommended default value for tws is 0.4 seconds (0xa0h). note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w tws7 tws6 tws5 tws4 tws3 tws2 tws1 tws0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 10100000 i 2 c address: 0x2b h
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 51 of 75 ath this register sets the threshold for wake - up (motion detect) interrupt is set. the kx022 will s hip from the factory with this value set to correspond to a change in acceleration of 0.5g . note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w ath7 ath6 ath5 ath 4 ath3 ath2 ath1 ath0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00001000 i 2 c address: 0x30h tilt_angle_ll this register sets the low level threshold for tilt angle detection. the kx022 ships from the factory with tilt angle set to a low threshold of 2 2 from horizontal. a different default tilt angle can be requested from the factory. note that the minimum suggested tilt angle is 10. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w ta7 ta6 ta5 ta4 ta3 ta2 ta1 ta0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0000110 0 i 2 c address: 0x32 h tilt_angle_hl this register sets the high level threshold for tilt angle detection . note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w hl7 hl6 hl5 hl4 hl3 hl2 hl1 hl0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00 101010 i 2 c address: 0x33 h
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 52 of 75 hyst_set this register sets the hysteresis that is placed in between the sc reen rotation states. the kx022 ships from the factory with hyst_set set to 15 of hysteresis. a different default hysteresis can be requested from the factory. note that when writing a new value to this regi ster the current values of res0 and res1 must be preserved. these values are set at the factory and must not change. note that to properly change the value of this register, the pc1 bit in ctrl_ reg1 must f irst be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w res 1 res 0 hyst5 hyst4 hyst3 hyst2 hyst1 hyst0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 000101 00 i 2 c address: 0x34h lp_cntl low power control s ets the number of samples of acc elerometer output to be averaged. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w reserved avc2 avc1 avc0 reserved reserved reserved reserved reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01001011 i 2 c address: 0x35 h avc <2:0> C averaging filter control, the default setting is 16 samples averaged 000 = no averaging 001 = 2 samples averaged 010 = 4 samples averaged 011 = 8 samples averaged 100 = 16 samples averaged (default) 101 = 32 samples averaged 110 = 64 samples averaged 111 = 128 samples averaged
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 53 of 75 buf_cntl1 read/write control register that controls the buffer sample threshold. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w - smp 6 smp 5 smp 4 smp 3 smp 2 smp 1 smp 0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000 i 2 c address: 0x3a h smp_th[6:0] sample threshold ; determines the number of samples that will trigger a watermark interrupt or will be saved prior to a trigger event. when buf_res=1, the maximum number of samples is 41; when buf_res=0, the maximum number of samples is 84. buffer model sample function bypass none fifo specifies how many buffer sample are needed to trigger a watermark interrupt. stream specifies how many buffer samples are needed to trigger a watermark interrupt. trigger specifies how many buffer samples before the trigger event are retained in th e buffer. filo specifies how m any buffer samples are needed to trigger a watermark interrupt. table 22 : sample threshold operation by buffer mode
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 54 of 75 buf_c ntl 2 read/write control register that controls sample buff er operation. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w b u fe b res bfie 0 0 0 b uf_ m1 b uf_ m0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000 i 2 c address: 0x3b h bufe controls activation of the sample buffer. bufe = 0 C sample buffer inactive bufe = 1 C sample buffer active b res determines the resolution of the acceleration data samples collected by the sample buffer. buf_res = 0 C 8 - bit samples are accumulated in the buffer buf_res = 1 C 16 - bit samples are accumulated in the buffer bfie buffer full interrupt enable bit bfie = 0 C buffer full interrupt disabled bfie = 1 C buffer full interrupt updated in ins2 buf_m1, buf_m0 selects the operating mode of the sample buffer per table 23 . buf_m1 buf_m0 mode description 0 0 fifo the buffer collects 84 sets of 8 - bit low re solution values or 41 sets of 16 - bit high resolution values and then stops collecting data, collecting new data only when the buffer is not full. 0 1 stream the buffer holds the last 84 sets of 8 - bit low re solution values or 41 sets of 16 - bit high resolution values. once the buffer is full, the oldest data is discarded to make room for newer data . 1 0 trigger when a trigger event occurs , the buffer holds the last data set o f smp[6:0] samples before the trigger event and then continues to collect data until full. new data is collected only when the buffer is not full. 1 1 fil o the buffer holds the last 84 sets of 8 - bit low re solution values or 41 sets of 16 - bit high resolution values. once the buffer is full, the oldest data is discarded to make room for newer data. r ead ing from the buffer in this mode will return the most r ecent data first . table 23 : selected buffer mode
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 55 of 75 buf_status_ 1 this register reports the status of the sample buffer. r/w r/w r/w r/w r/w r/w r/w r/w smp_lev7 smp_lev6 smp_lev5 smp_lev4 smp_lev3 smp_lev2 smp_lev1 smp_lev0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x3c h smp_lev[7:0] sample level ; reports the number of data bytes that have been stored in the sample buffer. when buf_res=1, this count will increase by 6 for each 3 - axis sample in the buffer; when buf_res=0, the count will increase by 3 for each 3 - axis sample. if this register reads 0, no data has been stored in the buffer. buf_status_ 2 this register reports the status of the sample buffer trigger function. r/w r/w r/w r/w r/ w r/w r/w r/w buf_trig 0 0 0 0 0 0 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x3d h buf_trig reports the status of the buffers trigger function if this mode has been selected. when using trigger mode, a buffer read should only b e performed after a trigger event. buf_clear latched buffer status information and the entire sample buffer are cleared when any data is written to this register. r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x3e h buf_read buffer output register r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x3fh
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 56 of 75 self_test when 0xca is written to this register, the mems self - test func tion is enabled. electrostatic - actuation of the accelerometer, results in a dc shift of the x, y and z axis outputs. writing 0x00 to this register will return the accelerometer to norma l operation. r/w r/w r/w r/w r/w r/w r/w r/w 1 1 0 0 1 0 1 0 rese t value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000 i 2 c address: 0x60h
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 57 of 75 embedded applications orientation detection feature the orientation detection feature of the kx022 will report changes in face up, face down, vertical and h orizontal orientation. this intelligent embedded algorithm considers very important factors that provide accurate orientation detection from low cost tri - axis accelerometers. factors such as: hysteresis, device orientation angle and delay time are descri bed below as these techniques are utilized inside the kx022 hysteresis a 45 tilt angle threshold seems like a good choice because it is halfway between 0 and 90. however, a problem arises when the user holds the device near 45. slight vibrations, n oise and inherent sensor error will cause the acceleration to go above and below the threshold rapidly and randomly, so the screen will quickly flip back and forth between the 0 and the 90 orientations. this problem is avoided in the kx022 by choosing a 30 threshold angle. with a 30 threshold, the screen will not rotate from 0 to 90 until the device is tilted to 60 (30 from 90). to rotate back to 0, the user must tilt back to 30, thus avoiding the screen flipping problem. this example essenti ally applies 15 of hysteresis in between the four s creen rotation states. table 24 shows the acceleration limits implemented for t = 30 . orientation x acceleration (g) y acceleration (g) 0/360 - 0.5 < a x < 0.5 a y > 0.866 90 a x > 0.866 - 0.5 < a y < 0.5 180 - 0.5 < a x < 0.5 a y < - 0.866 270 a x < - 0.866 - 0.5 < a y < 0.5 table 24 : acceleration at the four orientations with 15 of hysteresis the k x022 allows the user to change the amount of hysteresis in between the four screen rotation states. by simply writing to the hyst_set register, the user can adjust the amo unt of hysteresis up to 45 . the plot in figure 8 shows the typical amount of hysteresis applied for a given digital count value of hyst_set . ?
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 58 of 75 figure 8 : hyst_set vs hysteresis device orientation angle (aka tilt angle) to ensure that horizontal and vertical device orientation chang es are detected, even when it isnt in the ideal vertical orientation C where the angle in figure 9 is 90, the kx022 considers device orientation angle in its algorithm. figure 9 : devi ce orientation angle as the angle in figure 9 is decreased, the maximum gravitational acceleration on the x - axis or y - axis will also decrease. therefore, when the angle becomes small enough, the user will not be able to make the screen orientation change. when the device orientation angle approaches 0 (device is flat on a angle ? hyst_set vs hysteresis 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 hyst_set value (counts) hysteresis (+/- degrees) hysteresis
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 59 of 75 desk or table), a x = a y = 0g, a z = +1g, and there is no way to determine which way the screen should be oriented, the internal algorithm deter mines that the device is in either the face - up or face - down orientation, depending on the sign of the z - axis. the kx022 will only change the screen orientation when the orientation angle is above the factory - defaulted/user - defined threshold set in the til t_angle _ll register. equation 2 can be used to determine what value to write to the tilt_angle _ll register to set the device orientation angle. the value for tilt_angle_hl is preset at the factory but can be adju sted in special cases (e.g. to reduce the effect of transient g - variation such as when device is being moved rather than just being rotated). tilt_angle _ll (counts) = sin * (32 (counts/g) ) equation 2 : tilt angle threshold tilt timer the 8 - bit register, tilt_timer can be used to qualify changes in orientation. the kx022 does this by incrementing a counter with a size that is specified by the value in tilt_timer for each set of acceleration samples to verify that a change t o a new orientation state is maintained. a user defined output data rate (odr) determines the time period for each sample. equation 3 shows how to calculate the tilt_timer register value for a desired delay time. tilt_timer (co unts) = delay time (sec) x odr (hz) equation 3 : tilt position delay time
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 60 of 75 motion interrupt feature description the motion interrupt feature of the kx022 reports qualified changes in the high - pass filtered acceleration bas ed on the wake up (ath ) threshold. if the high - pass filtered acceleration on any axis is greater than the user - defin ed wake up threshold (ath ), the device has transitioned from an inactive state to an active state. equation 4 shows how to calculate the ath register value for a desired wake up threshold. note that this calculation varies based on the configured g - range of the part. ath (counts) = wake up threshold (g) x 16 (counts/g) equation 4 : wake up threshold an 8 - bit raw unsigned value represents a counter that permits the user to qualify each active/inactive state change. note that each wuf c timer count qualifies 1 (one) user - defined odr period (owuf). equation 5 shows h ow to calculate the wuf c register value for a desired wake up delay time. wu fc (counts) = wake up delay time (sec) x owuf (hz) equation 5 : wake up delay time the latched motion interrupt response algorithm works as following: w hile the part is in in active state, the algorithm evaluate s differential measurement between each new acceleration data point with the preceding one and evaluates it against the ath threshold. when the differential measurement is greater than at h threshol d , the wakeup counter start s the count. differential measurements are now calculated based on the difference between the current acceleration and the acceleration when the counter started. the part will report that motion has occurred at the end of the co unt assuming each differential measurement has remained above the threshold. if at any moment during the count the differential measurement falls below the threshold, the counter will stop the count and the part will remain in inactive state. to illustr ate how the algorithm works, consider the figure 10 below that shows the latched response of the motion detection algorithm with wuf timer (wufc) set to 10 counts. n ote how the difference between the acceleration sample marked in red and the one marked in green resulted in a differential measurements represented with orange bar being above the wuf threshold. at this point, the counter begins to count number of counts stored in wufc register and the wakeup algorithm will evaluate th e difference between each new acceleration measurement and the measurement marked in green that will remain a reference measurement for the duration of the counter count. at the end of the count, assuming all differential measurements were larger than wuf threshold, as is the case in the example showed in figure 10 , a motion event will be reported.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 61 of 75 figure 10 : latched motion interrupt response
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 62 of 75 directional tap detection feature description the direction al tap detection feature of the kx022 recognizes single and double tap inputs and reports the acceleration axis and direction that each tap occurred. eight performance parameters, as well as a user - selectable odr are used to configure the kx022 for a desi red tap detection response. performance index the directional tap tm detection algorithm uses low and high thresholds to help determine when a tap event has occurred. a tap event is detected when the previously described jerk summation exceeds the lo w threshold ( ttl ) for more than the tap detection low limit, but less than the tap detection high limit as contained in ftd . samples that exceed the high limit ( tth ) will be ignored. figure 11 shows an example of a single tap ev ent meeting the performance index criteria. figure 11 : jerk summation vs threshold ttl : sampled data 3.14 3.15 3.16 3.17 3.18 3.19 3.2 3.21 0 20 40 60 80 100 120 140 160 180 calculated performance index time(sec) jerk (counts) pi
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 63 of 75 single tap detection the latency timer ( tlt ) sets the time period that a tap event will only be characterized as a single tap. a second tap ha s to occur outside of the latency timer. if a second tap occurs inside the latency time, it will be ignored as it occurred too quickly. the single tap will be reported at the end of the tws . figure 12 shows a single tap event me eting the pi, latency and window requirements. figure 12 : single directional taptm timing tws tlt ttl 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 0 20 40 60 80 100 120 140 160 calculated performance index time(sec) jerk (counts) pi
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 64 of 75 double tap detection an event can be characterized as a double tap if the second tap crosses up the performance index (ttl) inside t he tws period and ends outside the tdtc. this means that the tdtc determines the minimum time separation that must exist between the two taps of a double tap event. similar to the single tap, the first tap event must exceed the performance index for the time limit contained in ftd. also, the duration when the first and second events combined exceed the performance index should not exceed std. the double tap will be reported at the end of the second tlt . figure 13 shows a double tap event meeting the pi, latency and window requirements. figure 13 : double directional tap tm timing
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 65 of 75 sample buffer feature description the sample buffer feature of the kx022 accumulates and outputs acceleration data based on how it is configured. there are 4 buffer modes available, and samples can be accumulated a t either low (8 - bit) or high (16 - bit) resolution. acceleration data is collected at the odr specified by osaa:osad in the output data control register. each buffer mo de accumulates data, reports data, and interacts with status indicators in a slightly different way. fifo mode data accumulation sample collection stops when the buffer is full. data reporting data is reported with the oldest byte of the oldest sample first (x_l or x based on resolution). status indicators a watermark interrupt occurs when the number of samples in the buffer reaches the sample threshold . the watermark interrupt stays active until the buffer contains less than this n umber of samples. this can be accomplished through clearing the buffer or explicitly reading greater than smpx samples (calculated with equation 6 ). buf_res =0 : smpx = smp_lev[7:0] / 3 C smp_th[6:0] b uf_res =1 : smpx = smp_lev[7:0] / 6 C smp_th[6:0] equation 6 : samples above sample threshold stream mode data accumulation sample collection continues when the buffer is full; older data is discarded to make room for new er data. data reporting data is reported with the oldest sample first (uses fifo read pointer). status indicators a watermark interrupt occurs when the number of samples in the buffer reaches the sample threshold . the watermark interrupt stay s active until the buffer contains less than this number of samples. this can be accomplished through clearing the buffer or explicitly reading greater than smpx samples (calculated with equation 1 ).
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 66 of 75 trigger mode data accumulation when a physical interrupt is caused by one of the digital engines, the trigger event is asserted and smp[6:0] samples prior to the event are retained. sample collection continues until the buffer is full. data reporting data is reported with the oldest sample first (uses fifo read pointer). status indicators when a physical interrupt occurs and there are at least smp[6:0] samples in the buffer, buf_trig in buf_status_reg2 is asserted. filo mode data accumulation sample collection continues when the buffer is full; older data is discarded to make room for newer data. data reporting data is reported with the newest byte of the newest sample first (z_h or z based on resolution). status indicators a watermark interrupt occur s when the number of samples in the buffer reaches the sample threshold . the watermark interrupt stays active until the buffer contains less than this number of samples. this can be accomplished through clearing the buffer or explicitly reading greater than smpx samples (calculated with equation 1 ). buffer operation the following diagrams illustrate the operation of the buffer conceptually. actual physical implementation has been abstracted to offer a simplified e xplanation of how the different buffer modes operate. figu re 14 represents a high - resolution 3 - axis sampl e within the buffer. figure 15 - figure 23 represent a 10 - sample version of the buffer (for simplicity), with sample threshold set to 8. regardless of the selected mode, the buffer fills sequentially, one byte at a time. figu re 14 shows o ne 6 - byte data sample. note the location of the filo read pointer versus that of the fifo read pointer.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 67 of 75 index byte 0 x_l ? ? ? figu re 14 : one buffer sample regardless of the selected mode, the buffer fills sequentially, one sample at a time. note in figure 15 the location of the filo read pointer versus that of th e fifo read pointer. the buffer write pointer shows where the next sample will be written to the buffer. index sample 0 data0 1 data1 2 data2 buffer write pointer 4 5 6 7 8 9 figure 15 : buffer filling
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 68 of 75 the buffer continues to fill sequentially until the sample threshold is reached. note in figure 16 the location of the filo read pointer versus that of the fifo read pointer. index sample 0 data0 1 data1 2 data2 3 data3 4 data4 5 data5 6 data6 buffer write pointer 8 9 figure 16 : buffer approaching sample threshold in fifo, stream, and filo modes, a watermark interrupt is issued when the number of samples in the buffer reaches the sample threshold . in trigger mode, this is the point where the oldest data in the buffer is discarded to make room for newer data. index sample 0 data0 1 data1 2 data2 3 data3 4 data4 5 dat a5 6 data6 7 data7 buffer write pointer 9 figure 17 : buffer at sample threshold
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 69 of 75 in trigger mode, data is accumulated in the buffer sequentially until the sample threshold is reached. once the sample threshold is reached, the oldest samples are discarded when new samples a re collected. note in figure 18 how data0 was thrown out to make room for data8. index sample 0 data1 1 data2 2 data3 3 data4 4 data5 5 data6 6 data7 trigger write pointer 8 9 figure 18 : additional data prior to trigger event after a trigger event occurs, the buffer no l onger discards the oldest samples, and instead begins accumulating samples sequentially until full. the buffer then stops collecting samples, as s een in figure 19 . this results in the buffer holding smp_th[6:0] sa mples prior to the trigger event, and smpx samples after the trigger event. index sample 0 data1 1 data2 2 data3 3 data4 4 data5 5 data6 6 data7 7 data8 8 data9 9 data10 figure 19 : additional data after trigger event
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 70 of 75 in fifo, stream, filo, and trigger (after a trigge r event has occurred) modes, the buffer continues filling sequentially after the sample threshold is reached. sample accumulation after the buffer is full depends on the selected operation mode. fifo and trigger modes stop accumulating samples when the b uffer is full, and stream and filo modes begin discarding the oldest data when new samples are accumulated. index sample 0 data0 1 data1 2 data2 3 data3 4 data4 5 data5 6 data6 7 data7 8 data8 9 data9 figure 20 : buffer full after the buffer has been filled in filo or stream mode, t he oldest samples are discarded when new samples a re collected. note in figure 21 how data0 was thrown out to make room for data10. index sample 0 data1 1 data2 2 data3 3 data4 4 data5 5 data6 6 data7 7 data8 8 data9 9 data10 figure 21 : buffer full C additional sample accumulation in stream or filo mode
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 71 of 75 in fifo, stream, or trigger mode, reading one sample from th e buffer will remove the oldest sample and effectively shift the entire buffer c ontents up, as seen in figure 22 . index sample 0 data1 1 data2 2 data3 3 data4 4 data5 5 data6 6 data7 7 data8 8 data9 buffer write pointer figure 22 : fifo read from full buffer in filo mode, reading one sample from the buffer will remove the newest sample and leave the older sample s untouched, as seen in figure 23 . index sample 0 data0 1 data1 2 data2 3 data3 4 data4 5 data5 6 data6 7 data7 8 data8 buffer write pointer figure 23 : filo read from full buffer
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 72 of 75 notice precaution on using kionix products 1. our products are designed and manufactured for application in ordinary electronic equipment (such as av equipment, oa equipment, telecommunic ation equipment, home electronic appliances, amusement equipment, etc.). if you intend to use our products in devices requiring extremely high reliability (such as medical equipment (note 1), transport equipment, traffic equipment, aircraft/spacecraft, nuc lear power controllers, fuel controllers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property (specific applications), please consult wi th the kionix sales representative in advance. unless otherwise agreed in writing by kionix in advance, kionix shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ki onixs products for specific applications. (note1) medical equipment classification of the specific applications japan usa eu china class responsible or liable for any damages, expenses or losses arising from the use of any kionixs products under any special or extraordinary environments or conditions. if you intend to use our products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc. , prior to use, must be necessary: a) use of our products in any types of liquid, including water, oils, chemicals, and organic solvent s b) use of our products outdoors or in places where the products are exposed to direct sunlight or dust c) use of our products in places where the products are exposed to sea wind or corrosive gases, including cl2, h2s, nh3, so2, and no2 d) use of our products in places where the products are exposed to static electricity or electromagnetic waves e) use of our products in proximity to heat - producing components, plastic cords, or other flammable items f) sealing or coating our products with resin or other coating material s g) use of our products without cleaning residue of flux (even if you use no - clean type fluxes, cleaning residue of flux is recommended); or washing our products by using water or water - soluble cleaning agents for cleaning residue after soldering h) use of the products in places subject to dew condensation 4. the products are not subject to radiation - proof design. 5. please verify and confirm characteristics of the final or mounted products in using the products. 6. in particular, if a transient load (a large amount of l oad applied in a short period of time, such as pulse. is applied, confirmation of performance characteristics after on - board mounting is strongly recommended. avoid applying
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 73 of 75 power exceeding normal rated power; exceeding the power rating under steady - state loading condition may negatively affect product performance and reliability. 7. de - rate power dissipation (pd) depending on ambient temperature (ta). when used in sealed area, confirm the actual ambient temperature. 8. confirm that operation temperature is withi n the specified range described in the product specification. 9. kionix shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in this document. precaution for mounting / circuit board design 1. when a hig hly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product performance and reliability. 2. in principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the kionix representative in advance. for details, please refer to kionix mounting specification . precautions regarding application examples and external circuits 1. if change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the characteristics of the products and external components, including transient characteristics, as well as static characteristics. 2. you agree that application notes, reference designs, and associated data and information containe d in this document are presented only as guidance for products use. therefore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. kionix shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. precaution for electrostatic this product is electrostatic sensitive pro duct, which may be damaged due to electrostatic discharge. please take proper caution in your manufacturing process and storage so that voltage exceeding the products maximum rating will not be applied to products. please take special care under dry condit ion (e.g. grounding of human body / equipment / solder iron, isolation from charged objects, setting of ionizer, friction prevention and temperature / humidity control). precaution for storage / transportation 1. product performance and soldered connections may deteriorate if the products are stored in the places where: a) the products are exposed to sea winds or corrosive gases, including cl2, h2s, nh3, so2, and no2 b) the temperature or humidity exceeds those recommended by kionix c) the products are exposed to dire ct sunshine or condensation d) the products are exposed to high electrostatic 2. even under kionix recommended storage condition, solderability of products out of recommended storage time period may be degraded. it is strongly recommended to confirm solderabilit y before using products of which storage time is exceeding the recommended storage time period. 3. store / transport cartons in the correct direction, which is indicated on a carton with a symbol. otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. use products within the specified time after opening a humidity barrier bag. baking is required before using products of which storage time is exceeding the recommended storage time period.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 74 of 75 precaution for product label qr code p rinted on kionix products label is for kionix s internal use only. precaution for disposition when disposing products please dispose them properly using an authorized industry waste company. precaution for foreign exchange and foreign trade act since our products might fall under controlled goods prescribed by the applicable foreign exchange and foreign trade act, please consult with kionix representative in case of export. precaution regarding intellectual property rights 1. all information and data includ ing but not limited to application example contained in this document is for reference only. kionix does not warrant that foregoing information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. kionix shall not be in any way responsible or liable for infringement of any intellectual property rights or other damages arising from u se of such information or data. 2. no license, express ly or implied, is granted hereby under any intellectual property rights or other rights of kionix or any third parties with respect to the information contained in this document. other precaution 1. this document may not be reprinted or reproduced, in whole or in part, without prior written consent of kionix . 2. the products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of kionix . 3. in no event shall you use in any way whatsoever the products and the re lated technical information contained in the products or this document for any military purposes, including but not limited to, the development of mass - destruction weapons. 4. the proper names of companies or products described in this document are trademarks or registered trademarks of kionix , its affiliated companies or third parties. general precaution 1. before you use our products, you are requested to carefully read this document and fully understand its contents. kionix shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any kionix s products against warning, caution or note contained in this document. 2. all information contained in this document is current as of the issuing date and subject to change wi thout any prior notice. before purchasing or using kionix s products, please confirm the latest information with a kionix sales representative. 3. the information contained in this document is provided on an as is basis and kionix does not warrant that all information contained in this document is accurate and/or error - free. kionix shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or concerning such inform ation.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kx 022 - 1020 rev. 11.0 10 - sep - 15 36 thornwood dr. C ithaca, ny 14850 ? 2015 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 www.kionix.com - info@kionix.com page 75 of 75 revision history revision description date 1.0 initial release 12 - sep t - 201 3 1.1 added lp_cntl accelerometer output averaging register, updated test spec limits table 5 and i2c timing table 8 02 - oct - 2013 2.0 added reference to flexset? performance optimization , updated reference to osa in odcntl for xout_l register. 19 - nov - 2013 3.0 updated default values for tspp, tscp, odcntl 03 - dec - 2013 4.0 added min and max s elf - test limits to table 1 08 - jan - 2014 5.0 improved high resolution and low power mode descriptions , corrected test specification limits table 5 . 16 - jan - 2014 6.0 revised package dimensions. 05 - sep - 2014 7.0 revised accelerometer outputs table 16 - sep - 2014 8.0 updated package drawing 10 - oct - 2014 9.0 revised odr settings and current profile 08 - dec - 2014 10.0 added power - on procedure details. updated figure 1 . updated motion interrupt plot and feature. updated double - tap detection plot and description. fixed factory value set for tilt_angle_ll. 01 - apr - 2015 11.0 updated table 12 : acceler ation (g) calculation updated current profile plot and table updated por section updated rohs compliance. added reach compliance. updated reading from / writing to kx023 8 - bit register section updated i2c timing diagram updated i2c address table added note to writing to 8 - bit register i2c section updated wake up threshold equation updated 3 - wire and 4 - wire read and write registers added notice section 09 - sep - 2015 "kionix" is a registered trademark of kionix, inc. products described herein are protect ed by patents issued or pending. no license is granted by implication or otherwise under any patent or other rights of kionix. the information contained herein is believed to be accurate and reliable but is not guaranteed. kionix does not assume responsibi lity for its use or distribution. kionix also reserves the right to change product specifications or discontinue this product at any time without prior notice. this publication supersedes and replaces all information previously supplied.

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